1. Field of the Invention
The present invention relates to a three-input analog multiplier and more particularly, to a three-input multiplier for multiplying three input signals and a multiplier core circuit used therefor, which is suitable for a semiconductor integrated circuit and operable at a supply voltage as low as approximately 1 V.
2. Description of the Prior Art
In general, a conventional three-input multiplier is comprised of a differential circuit and emitter-coupled pairs of bipolar transistors whose collectors are cross-coupled with each other. The emitter-coupled pairs are cascaded at a multistage and the differential circuit is connected in series to the first or last stage of the emitter-coupled pairs.
One of the conventional three-input multipliers is disclosed in detail in IEEE Journal of Solid-State Circuits, VOL. SC-16, NO.4, pp.392-399, August 1981, which is shown in FIG. 1.
As shown in FIG. 1, this conventional three-input multiplier is comprised of a first pair of npn bipolar transistors Q101 and Q102, a second pair of npn bipolar transistors Q103 and Q104, a third pair of npn bipolar transistors Q105 and Q106, a fourth pair of npn bipolar transistors Q107 and Q108, a fifth pair of npn bipolar transistors Q109 and Q110 and a constant current sink 101 sinking a constant current I.sub.0.
In a first stage, emitters of the transistors Q101 and Q102 are coupled together and emitters of the transistors Q103 and Q104 are coupled together. Collectors of the transistors Q101 and Q103 are connected to each other and collectors of the transistors Q102 and Q104 are connected to each other. Bases of the transistors Q102 and Q103 are coupled together, and bases of the transistors Q101 and Q104 are coupled together.
A differential output current I.sup.+ is derived from the coupled collectors of the transistors Q101 and Q103. Another differential output current I.sup.- is derived from the coupled collectors of the transistors Q102 and Q104. A differential output current .DELTA.I of this three-input multiplier is given by the difference between these two differential output currents I.sup.+ and I.sup.-, i.e., .DELTA.I=I.sup.+ -I.sup.-.
A first input voltage V.sub.x is applied across the coupled bases of the transistors Q102 and Q103 and those of the transistors Q101 and Q104.
In a second stage, similarly, emitters of the transistors Q105 and Q106 are coupled together and emitters of the transistors Q107 and Q108 are coupled together. Collectors of the transistors Q105 and Q107 are connected to each other and collectors of the transistors Q106 and Q108 are connected to each other. The coupled collectors of the transistors Q105 and Q107 are connected to the coupled emitters of the transistors Q101 and Q102. The coupled collectors of the transistors Q106 and Q108 are connected to the coupled emitters of the transistors Q103 and Q104. Bases of the transistors Q105 and Q108 are coupled together and bases of the transistors Q106 and Q107 are coupled together.
A second input voltage V.sub.y is applied across the coupled bases of the transistors Q106 and Q107 and those of the transistors Q105 and Q108.
In a third stage, emitters of the transistors Q109 and Q110 are coupled together to be connected to a terminal of the constant current sink 101. The other end of the constant current sink 101 is connected to the ground. A collector of the transistor Q109 is connected to the coupled emitters of the transistors Q105 and Q106. A collector of the transistor Q110 is connected to the coupled emitters of the transistors Q107 and Q108.
A third input voltage V.sub.z is applied across a base of the transistor Q109 and a base of the transistor Q110.
As clearly seen from FIG. 1, the third, fourth, and fifth emitter-coupled pairs of the transistors Q105, Q106, Q107, Q108, Q109, and Q110 constitute a well-known Gilbert multiplier cell. Therefore, it can be said that the conventional three-input multiplier in FIG. 1 is comprised of the Gilbert multiplier cell and the first and second emitter-coupled pairs of the transistors Q101, Q102, Q103, and Q104 whose collectors are cross-coupled.
In general, supposing that a collector current I.sub.c and a base-to-emitter voltage V.sub.BE of a bipolar transistor satisfy the exponential law, the collector current I.sub.c is expressed by the following equation (1). ##EQU1##
In the equation (1) I.sub.S is the saturation current, and V.sub.T is the thermal voltage expressed as V.sub.T =kT/q, where k is Boltzmann's constant, T is absolute temperature in degrees Kelvin and q is the charge of an electron.
When a bipolar transistor is in a normal operation where the base-to-emitter voltage V.sub.BE is approximately 600 mV, the exponential term "exp(V.sub.BE /V.sub.T)" has a value of approximately e.sup.10. Therefore, the constant term "-1" may be ignored. As a result, the equation (1) can be rewritten to the following equation (2). ##EQU2##
Here, if collector currents of the transistors Q101 to Q110 are defined as I.sub.C1, I.sub.C2, I.sub.C3, I.sub.C4, I.sub.C5, I.sub.C6, I.sub.C7, I.sub.C8, I.sub.C9, and I.sub.C10, respectively, each of these collector currents can be expressed in the same form as shown by the equation (2).
On the other hand, since the differential output current .DELTA.I of the conventional three-input multiplier in FIG. 1 is equal to a differential output current of the first and second emitter-coupled pairs of the transistors Q101 to Q104 whose collectors are cross-coupled, the current .DELTA.I is expressed by the following equation (3) as ##EQU3## where .alpha..sub.F is the dc common-base current gain factor of an npn bipolar transistor.
The term "(I.sub.C5 +I.sub.C7)" in the equation (3) is derived from the fact that the current flowing through the coupled emitters of the transistors Q101 and Q102 is expressed as (I.sub.C5 +I.sub.C7) Similarly, the term "(I.sub.C6 +I.sub.C8)" in the equation (3) is derived from the fact that the current flowing through the coupled emitters of the transistors Q103 and Q104 is expressed as (I.sub.C6 +I.sub.C8).
The collector currents I.sub.C5, I.sub.C6, I.sub.C7, and I.sub.C8 have the following relationship as ##EQU4##
The collector currents I.sub.C9 and I.sub.C10 have the following relationship as ##EQU5##
Substitution of the equations (4) and (5) into the equation (3) gives the following equation (6). ##EQU6##
Here, tanh(x) can be approximated in small signal applications as tanh(x)=x-(1/3)x.sup.3 + . . . , (x&lt;&lt;1). Therefore, the above equation (6) can be approximated to the following equation. ##EQU7##
It is seen from the equation (7) that the differential output current .DELTA.I of the conventional three-input multiplier in FIG. 1 is proportional to the product (V.sub.x .circle-solid.V.sub.y .circle-solid.V.sub.z) of the three input voltages V.sub.x, V.sub.y, and V.sub.z when the input voltages V.sub.x, V.sub.y, and V.sub.z are all small. This means that the circuit in FIG. 1 serves as a three-input multiplier for the three input voltages V.sub.x, V.sub.y, and V.sub.z.
In general, a multiplier is an essential functional block in analog signal applications. It is convenient that if three input voltages are available in a multiplier because the number of necessary multipliers can be decreased.
In recent years, there has been the increasing need for analog multipliers operable at a low supply voltage. However, the conventional three-input multiplier as shown in FIG. 1 is unable to operate normally if the power supply voltage is decreased. This is because the conventional three-input multiplier as shown in FIG. 1 includes three stacked stages of the differential transistor pairs.